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Condensed Matter > Materials Science
Title: Spatially resolved dielectric loss at the Si/SiO$_2$ interface
(Submitted on 23 Jun 2023 (v1), last revised 5 Apr 2024 (this version, v2))
Abstract: The Si/SiO$_2$ interface is populated by isolated trap states which modify its electronic properties. These traps are of critical interest for the development of semiconductor-based quantum sensors and computers, as well as nanoelectronic devices. Here, we study the electric susceptibility of the Si/SiO$_2$ interface with nm spatial resolution using frequency-modulated atomic force microscopy to measure a patterned dopant delta-layer buried 2 nm beneath the silicon native oxide interface. We show that surface charge organization timescales, which range from 1-150 ns, increase significantly around interfacial states. We conclude that dielectric loss under time-varying gate biases at MHz and sub-MHz frequencies in metal-insulator-semiconductor capacitor device architectures is highly spatially heterogeneous over nm length scales.
Supplemental GIFs can be found at this https URL
Submission history
From: Megan Cowie [view email][v1] Fri, 23 Jun 2023 17:55:35 GMT (8384kb,D)
[v2] Fri, 5 Apr 2024 01:20:20 GMT (3944kb)
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