Hardware Architecture

New submissions

• New submissions
• Cross-lists
• Replacements

New submissions for Fri, 10 May 24

[1]  arXiv:2405.05480 [pdf, other]

Title: FloorSet - a VLSI Floorplanning Dataset with Design Constraints of Real-World SoCs

Authors: Uday Mallappa, Hesham Mostafa, Mikhail Galkin, Mariano Phielipp, Somdeb Majumdar

Comments: 10 pages, 11 figures

Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG)

Floorplanning for systems-on-a-chip (SoCs) and its sub-systems is a crucial and non-trivial step of the physical design flow. It represents a difficult combinatorial optimization problem. A typical large scale SoC with 120 partitions generates a search-space of nearly 10E250. As novel machine learning (ML) approaches emerge to tackle such problems, there is a growing need for a modern benchmark that comprises a large training dataset and performance metrics that better reflect real-world constraints and objectives compared to existing benchmarks. To address this need, we present FloorSet - two comprehensive datasets of synthetic fixed-outline floorplan layouts that reflect the distribution of real SoCs. Each dataset has 1M training samples and 100 test samples where each sample is a synthetic floor- plan. FloorSet-Prime comprises fully-abutted rectilinear partitions and near-optimal wire-length. A simplified dataset that reflects early design phases, FloorSet-Lite comprises rectangular partitions, with under 5 percent white-space and near-optimal wire-length. Both datasets define hard constraints seen in modern design flows such as shape constraints, edge-affinity, grouping constraints, and pre-placement constraints. FloorSet is intended to spur fundamental research on large-scale constrained optimization problems. Crucially, FloorSet alleviates the core issue of reproducibility in modern ML driven solutions to such problems. FloorSet is available as an open-source repository for the research community.

Cross-lists for Fri, 10 May 24

[2]  arXiv:2405.05540 (cross-list from cs.NI) [pdf, ps, other]

Title: Shape-Optimized Electrooptic Beam Scanners: Experiment

Authors: Jennifer C. Fang, M. J. Kawas, J. Zou, V. Gopalan, T. E. Schlesinger, Daniel D. Stancil

Comments: 3 pages, 3 figures. IEEE Photonics Technology Letters. Author Jennifer C. Fang is currently known as Jennifer Andreoli-Fang

Journal-ref: IEEE Photonics Technology Letters ( Volume: 11, Issue: 1, January 1999)

Subjects: Networking and Internet Architecture (cs.NI); Hardware Architecture (cs.AR)

A new horn-shaped electrooptic scanner is described with significantly improved scanning sensitivity over rectangular- shaped devices. In the new device, the shape of the scanner is chosen to follow the trajectory of the beam. An example design is described that exhibits a factor of two larger scanning sensitivity than a rectangular device with comparable maximum scanning angle. Beam propagation simulations and measurements on an experimental device verify the scanner performance.

[3]  arXiv:2405.05590 (cross-list from cs.CR) [pdf, other]

Title: TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans

Authors: Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F.Y. Young, Johann Knechtel

Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR); Machine Learning (cs.LG)

Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many security threats, like piracy of IC intellectual property or insertion of hardware Trojans, i.e., malicious circuit modifications.
In this work, we proactively and systematically protect the physical layouts of ICs against post-design insertion of Trojans. Toward that end, we propose TroLLoc, a novel scheme for IC security closure that employs, for the first time, logic locking and layout hardening in unison. TroLLoc is fully integrated into a commercial-grade design flow, and TroLLoc is shown to be effective, efficient, and robust. Our work provides in-depth layout and security analysis considering the challenging benchmarks of the ISPD'22/23 contests for security closure. We show that TroLLoc successfully renders layouts resilient, with reasonable overheads, against (i) general prospects for Trojan insertion as in the ISPD'22 contest, (ii) actual Trojan insertion as in the ISPD'23 contest, and (iii) potential second-order attacks where adversaries would first (i.e., before Trojan insertion) try to bypass the locking defense, e.g., using advanced machine learning attacks. Finally, we release all our artifacts for independent verification [2].

Replacements for Fri, 10 May 24

[4]  arXiv:2106.11840 (replaced) [pdf, other]

Title: Quantum Computing - A new scientific revolution in the making

Authors: Koen Bertels, Emma Turki, Tamara Sarac, Aritra Sarkar, Imran Ashraf

Comments: 16 pages, 5 figures

Subjects: Quantum Physics (quant-ph); Hardware Architecture (cs.AR)

[5]  arXiv:2306.14882 (replaced) [pdf, other]

Title: Citadel: Real-World Hardware-Software Contracts for Secure Enclaves Through Microarchitectural Isolation and Controlled Speculation

Authors: Jules Drean, Miguel Gomez-Garcia, Fisher Jepsen, Thomas Bourgeat, Srinivas Devadas

Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)

• New submissions
• Cross-lists
• Replacements