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Hardware Architecture

Authors and titles for recent submissions

[ total of 26 entries: 1-25 | 26 ]
[ showing 25 entries per page: fewer | more | all ]

Fri, 26 Apr 2024

[1]  arXiv:2404.16629 [pdf, other]
Title: Implementing and Optimizing the Scaled Dot-Product Attention on Streaming Dataflow
Authors: Gina Sohn, Nathan Zhang, Kunle Olukotun
Comments: 4 pages, 3 figures
Subjects: Hardware Architecture (cs.AR)
[2]  arXiv:2404.16317 [pdf, other]
Title: FLAASH: Flexible Accelerator Architecture for Sparse High-Order Tensor Contraction
Authors: Gabriel Kulp, Andrew Ensinger, Lizhong Chen
Comments: 10 pages, 3 figures
Subjects: Hardware Architecture (cs.AR); Machine Learning (cs.LG)
[3]  arXiv:2404.16158 [pdf, other]
Title: The Feasibility of Implementing Large-Scale Transformers on Multi-FPGA Platforms
Authors: Yu Gao, Juan Camilo Vega, Paul Chow
Comments: 33 pages, 24 figures
Subjects: Hardware Architecture (cs.AR); Distributed, Parallel, and Cluster Computing (cs.DC); Machine Learning (cs.LG)
[4]  arXiv:2404.16256 (cross-list from cs.CR) [pdf, other]
Title: Probabilistic Tracker Management Policies for Low-Cost and Scalable Rowhammer Mitigation
Authors: Aamer Jaleel, Stephen W. Keckler, Gururaj Saileshwar
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)
[5]  arXiv:2404.16156 (cross-list from quant-ph) [pdf, other]
Title: Guardians of the Quantum GAN
Authors: Archisman Ghosh, Debarshi Kundu, Avimita Chatterjee, Swaroop Ghosh
Comments: 11 pages, 10 figures
Subjects: Quantum Physics (quant-ph); Hardware Architecture (cs.AR); Cryptography and Security (cs.CR); Machine Learning (cs.LG)

Thu, 25 Apr 2024

[6]  arXiv:2404.15823 [pdf, other]
Title: A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator
Authors: Oliver Bause, Paul Palomero Bernardo, Oliver Bringmann
Comments: accepted at MBMV 2024 - 27. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
[7]  arXiv:2404.15819 [pdf, other]
Title: APACHE: A Processing-Near-Memory Architecture for Multi-Scheme Fully Homomorphic Encryption
Authors: Lin Ding, Song Bian, Penggao He, Yan Xu, Gang Qu, Jiliang Zhang
Subjects: Hardware Architecture (cs.AR)
[8]  arXiv:2404.15733 [pdf, other]
Title: BlissCam: Boosting Eye Tracking Efficiency with Learned In-Sensor Sparse Sampling
Authors: Yu Feng, Tianrui Ma, Yuhao Zhu, Xuan Zhang
Subjects: Hardware Architecture (cs.AR)
[9]  arXiv:2404.15510 [pdf, other]
Title: NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator
Authors: Kaustubh Shivdikar, Nicolas Bohm Agostini, Malith Jayaweera, Gilbert Jonatan, Jose L. Abellan, Ajay Joshi, John Kim, David Kaeli
Comments: Visit this https URL for WebGUI based simulations
Subjects: Hardware Architecture (cs.AR); Distributed, Parallel, and Cluster Computing (cs.DC); Machine Learning (cs.LG); Neural and Evolutionary Computing (cs.NE)
[10]  arXiv:2404.15621 (cross-list from cs.ET) [pdf, ps, other]
Title: Layer Ensemble Averaging for Improving Memristor-Based Artificial Neural Network Performance
Authors: Osama Yousuf, Brian Hoskins, Karthick Ramu, Mitchell Fream, William A. Borders, Advait Madhavan, Matthew W. Daniels, Andrew Dienstfrey, Jabez J. McClelland, Martin Lueker-Boden, Gina C. Adam
Subjects: Emerging Technologies (cs.ET); Hardware Architecture (cs.AR); Machine Learning (cs.LG); Image and Video Processing (eess.IV)

Wed, 24 Apr 2024

[11]  arXiv:2404.15185 [pdf, other]
Title: PIVOT- Input-aware Path Selection for Energy-efficient ViT Inference
Authors: Abhishek Moitra, Abhiroop Bhattacharjee, Priyadarshini Panda
Comments: Accepted to 61st ACM/IEEE Design Automation Conference (DAC '24), June 23--27, 2024, San Francisco, CA, USA (6 Pages)
Subjects: Hardware Architecture (cs.AR)
[12]  arXiv:2404.14769 [pdf, ps, other]
Title: A high-level synthesis approach for precisely-timed, energy-efficient embedded systems
Authors: Yuchao Liao, Tosiron Adegbija, Roman Lysecky
Comments: Accepted at IGSC 2021, published in Sustainable Computing: Informatics and Systems (SUSCOM) 2022
Journal-ref: Sustainable Computing: Informatics and Systems 35 (2022): 100741
Subjects: Hardware Architecture (cs.AR)
[13]  arXiv:2404.14632 [pdf, other]
Title: Workload-Aware Hardware Accelerator Mining for Distributed Deep Learning Training
Authors: Muhammad Adnan, Amar Phanishayee, Janardhan Kulkarni, Prashant J. Nair, Divya Mahajan
Subjects: Hardware Architecture (cs.AR); Distributed, Parallel, and Cluster Computing (cs.DC)
[14]  arXiv:2404.14617 [pdf, other]
Title: TDRAM: Tag-enhanced DRAM for Efficient Caching
Authors: Maryam Babaie, Ayaz Akram, Wendy Elsasser, Brent Haukness, Michael Miller, Taeksang Song, Thomas Vogelsang, Steven Woo, Jason Lowe-Power
Subjects: Hardware Architecture (cs.AR)
[15]  arXiv:2404.15260 (cross-list from quant-ph) [pdf, other]
Title: Distributed Architecture for FPGA-based Superconducting Qubit Control
Authors: Neelay Fruitwala, Gang Huang, Yilun Xu, Abhi Rajagopala, Akel Hashim, Ravi K. Naik, Kasra Nowrouzi, David I. Santiago, Irfan Siddiqi
Comments: 10 pages, 13 figures
Subjects: Quantum Physics (quant-ph); Hardware Architecture (cs.AR)
[16]  arXiv:2404.15204 (cross-list from cs.PL) [pdf, other]
Title: Towards a high-performance AI compiler with upstream MLIR
Authors: Renato Golin, Lorenzo Chelini, Adam Siemieniuk, Kavitha Madhu, Niranjan Hasabnis, Hans Pabst, Evangelos Georganas, Alexander Heinecke
Comments: 13 pages, 8 figures, presented at CGO C4ML 2024 & MLIR Workshop EuroLLVM 2024
Subjects: Programming Languages (cs.PL); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR); Distributed, Parallel, and Cluster Computing (cs.DC); Machine Learning (cs.LG)
[17]  arXiv:2404.14754 (cross-list from cs.LG) [pdf, other]
Title: Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning
Authors: Yuchao Liao, Tosiron Adegbija, Roman Lysecky, Ravi Tandon
Comments: Accepted at Great Lakes Symposium on VLSI 2024 (GLSVLSI 24)
Subjects: Machine Learning (cs.LG); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR)

Tue, 23 Apr 2024

[18]  arXiv:2404.14069 [pdf, ps, other]
Title: On the Systematic Creation of Faithfully Rounded Commutative Truncated Booth Multipliers
Authors: Theo Drane, Samuel Coward, Mertcan Temel, Joe Leslie-Hurd
Subjects: Hardware Architecture (cs.AR)
[19]  arXiv:2404.14010 [pdf, other]
Title: A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training
Authors: Sami Ben Ali (TARAN), Silviu-Ioan Filip (TARAN), Olivier Sentieys (TARAN)
Journal-ref: DATE 2024 - 27th IEEE/ACM Design, Automation and Test in Europe, Mar 2024, Valencia, Spain. pp.1-6
Subjects: Hardware Architecture (cs.AR)
[20]  arXiv:2404.13062 [pdf, other]
Title: EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration
Authors: Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
Subjects: Hardware Architecture (cs.AR); Neural and Evolutionary Computing (cs.NE)
[21]  arXiv:2404.13061 [pdf, other]
Title: FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning
Authors: Shang Wang, Deepak Ranganatha Sastry Mamillapalli, Tianpei Yang, Matthew E. Taylor
Comments: accepted by ISEDA2024
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG)
[22]  arXiv:2404.13049 [pdf, ps, other]
Title: DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators
Authors: Andrew B. Kahng, Zhiang Wang
Subjects: Hardware Architecture (cs.AR); Machine Learning (cs.LG)
[23]  arXiv:2404.14279 (cross-list from cs.CV) [pdf, other]
Title: Co-designing a Sub-millisecond Latency Event-based Eye Tracking System with Submanifold Sparse CNN
Authors: Baoheng Zhang, Yizhao Gao, Jingyuan Li, Hayden Kwok-Hay So
Comments: Accepted to CVPR 2024 workshop, AIS: Vision, Graphics, and AI for Streaming
Subjects: Computer Vision and Pattern Recognition (cs.CV); Hardware Architecture (cs.AR)
[24]  arXiv:2404.14110 (cross-list from eess.SY) [pdf, other]
Title: HomeLabGym: A real-world testbed for home energy management systems
Authors: Toon Van Puyvelde, Marie-Sophie Verwee, Gargya Gokhale, Mehran Zareh Eshghdoust, Chris Develder
Comments: 3 pages, 2 figures, conference
Subjects: Systems and Control (eess.SY); Hardware Architecture (cs.AR)
[25]  arXiv:2404.13477 (cross-list from cs.CR) [pdf, other]
Title: Leveraging Adversarial Detection to Enable Scalable and Low Overhead RowHammer Mitigations
Authors: Oğuzhan Canpolat, A. Giray Yağlıkçı, Ataberk Olgun, İsmail Emir Yüksel, Yahya Can Tuğrul, Konstantinos Kanellopoulos, Oğuz Ergin, Onur Mutlu
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)
[ total of 26 entries: 1-25 | 26 ]
[ showing 25 entries per page: fewer | more | all ]

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