We gratefully acknowledge support from
the Simons Foundation and member institutions.

Hardware Architecture

Authors and titles for recent submissions, skipping first 10

[ total of 29 entries: 1-10 | 11-20 | 21-29 ]
[ showing 10 entries per page: fewer | more | all ]

Mon, 27 May 2024 (continued, showing last 6 of 8 entries)

[11]  arXiv:2405.15380 [pdf, other]
Title: Full-stack evaluation of Machine Learning inference workloads for RISC-V systems
Authors: Debjyoti Bhattacharjee, Anmol, Tommaso Marinelli, Karan Pathak, Peter Kourzanov
Comments: RISC-V Summit Europe 2024
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
[12]  arXiv:2405.15537 (cross-list from cs.CR) [pdf, ps, other]
Title: Do Not Trust Power Management: Challenges and Hints for Securing Future Trusted Execution Environments
Authors: Owen Le Gonidec, Maria Méndez Real, Guillaume Bouffard, Jean-Christophe Prévotet
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR); Emerging Technologies (cs.ET)
[13]  arXiv:2405.15322 (cross-list from cs.CR) [pdf, other]
Title: Dishonest Approximate Computing: A Coming Crisis for Cloud Clients
Authors: Ye Wang, Jian Dong, Ming Han, Jin Wu, Gang Qu
Comments: 12 pages, 9 figures
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)
[14]  arXiv:2405.15184 (cross-list from cs.CR) [pdf, other]
Title: TrojanForge: Adversarial Hardware Trojan Examples with Reinforcement Learning
Authors: Amin Sarihi, Peter Jamieson, Ahmad Patooghy, Abdel-Hameed A. Badawy
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR); Machine Learning (cs.LG)
[15]  arXiv:2405.14978 (cross-list from eess.SP) [pdf, other]
Title: Analog or Digital In-memory Computing? Benchmarking through Quantitative Modeling
Authors: Jiacong Sun, Pouya Houshmand, Marian Verhelst
Subjects: Signal Processing (eess.SP); Hardware Architecture (cs.AR); Image and Video Processing (eess.IV)
[16]  arXiv:2405.13938 (cross-list from cs.LG) [pdf, other]
Title: eXmY: A Data Type and Technique for Arbitrary Bit Precision Quantization
Authors: Aditya Agrawal, Matthew Hedlund, Blake Hechtman
Subjects: Machine Learning (cs.LG); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR); Numerical Analysis (math.NA)

Fri, 24 May 2024 (showing first 4 of 5 entries)

[17]  arXiv:2405.13170 [pdf, other]
Title: FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
Authors: Jianming Tong, Anirudh Itagi, Prasanth Chatarasi, Tushar Krishna
Comments: 17 pages, 14 figures. International Symposium on Computer Architecture (ISCA), Jun 2024
Subjects: Hardware Architecture (cs.AR)
[18]  arXiv:2405.14209 (cross-list from cs.PF) [pdf, other]
Title: Exploring and Evaluating Real-world CXL: Use Cases and System Adoption
Authors: Jie Liu (1), Xi Wang (1), Jianbo Wu (1), Shuangyan Yang (1), Jie Ren (2), Bhanu Shankar (3), Dong Li (1) ((1) University of California, Merced, (2) William & Mary, (3) MemVerge, Inc)
Subjects: Performance (cs.PF); Hardware Architecture (cs.AR)
[19]  arXiv:2405.13927 (cross-list from cs.CR) [pdf, other]
Title: Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes
Authors: Bharadwaj Madabhushi, Sandip Kundu, Daniel Holcomb
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)
[20]  arXiv:2405.13858 (cross-list from cs.DC) [pdf, other]
Title: Carbon Connect: An Ecosystem for Sustainable Computing
Authors: Benjamin C. Lee, David Brooks, Arthur van Benthem, Udit Gupta, Gage Hills, Vincent Liu, Benjamin Pierce, Christopher Stewart, Emma Strubell, Gu-Yeon Wei, Adam Wierman, Yuan Yao, Minlan Yu
Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR); Emerging Technologies (cs.ET); Machine Learning (cs.LG)
[ total of 29 entries: 1-10 | 11-20 | 21-29 ]
[ showing 10 entries per page: fewer | more | all ]

Disable MathJax (What is MathJax?)

Links to: arXiv, form interface, find, cs, new, 2405, contact, help  (Access key information)