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Hardware Architecture

Authors and titles for recent submissions, skipping first 26

[ total of 12 entries: 1-12 ]
[ showing up to 26 entries per page: fewer | more ]

Fri, 17 May 2024

[1]  arXiv:2405.10170 [pdf, other]
Title: A Mess of Memory System Benchmarking, Simulation and Application Profiling
Authors: Pouya Esmaili-Dokht, Francesco Sgherzi, Valeria Soldera Girelli, Isaac Boixaderas, Mariana Carmin, Alireza Momeni, Adria Armejach, Estanislao Mercadal, German Llort, Petar Radojkovic, Miquel Moreto, Judit Gimenez, Xavier Martorell, Eduard Ayguade, Jesus Labarta, Emanuele Confalonieri, Rishabh Dubey, Jason Adlard
Comments: 17 pages
Subjects: Hardware Architecture (cs.AR)

Thu, 16 May 2024

[2]  arXiv:2405.08982 (cross-list from quant-ph) [pdf, other]
Title: Enabling Leakage Reduction via Fast and High-Fidelity Qutrit Readout
Authors: Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit Tannu
Subjects: Quantum Physics (quant-ph); Hardware Architecture (cs.AR)

Wed, 15 May 2024

[3]  arXiv:2405.08754 (cross-list from cs.DC) [pdf, ps, other]
Title: Hierarchical Resource Partitioning on Modern GPUs: A Reinforcement Learning Approach
Authors: Urvij Saroliya, Eishi Arima, Dai Liu, Martin Schulz
Comments: Published in: 2023 IEEE International Conference on Cluster Computing (CLUSTER)
Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR); Machine Learning (cs.LG)
[4]  arXiv:2405.08470 (cross-list from cs.DC) [pdf, other]
Title: Sparse MTTKRP Acceleration for Tensor Decomposition on GPU
Authors: Sasindu Wijeratne, Rajgopal Kannan, Viktor Prasanna
Comments: In 21st ACM International Conference on Computing Frontiers (CF '24), May 7-9, 2024, Ischia, Italy
Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR)

Tue, 14 May 2024

[5]  arXiv:2405.07518 [pdf, other]
Title: SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts
Authors: Raghu Prabhakar, Ram Sivaramakrishnan, Darshan Gandhi, Yun Du, Mingran Wang, Xiangyu Song, Kejie Zhang, Tianren Gao, Angela Wang, Karen Li, Yongning Sheng, Joshua Brot, Denis Sokolov, Apurv Vivek, Calvin Leung, Arjun Sabnis, Jiayu Bai, Tuowen Zhao, Mark Gottscho, David Jackson, Mark Luttrell, Manish K. Shah, Edison Chen, Kaizhao Liang, Swayambhoo Jain, Urmish Thakker, Dawei Huang, Sumti Jairath, Kevin J. Brown, Kunle Olukotun
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
[6]  arXiv:2405.07259 [pdf, other]
Title: CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool
Authors: Tanner Andrulis, Joel S. Emer, Vivienne Sze
Comments: Available at this https URL Published in ISPASS 2024
Subjects: Hardware Architecture (cs.AR)
[7]  arXiv:2405.06840 [pdf, other]
Title: MEIC: Re-thinking RTL Debug Automation using LLMs
Authors: Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang
Subjects: Hardware Architecture (cs.AR); Software Engineering (cs.SE)
[8]  arXiv:2405.07266 (cross-list from cs.ET) [pdf, other]
Title: Architecture-Level Modeling of Photonic Deep Neural Network Accelerators
Authors: Tanner Andrulis, Gohar Irfan Chaudhry, Vinith M. Suriyakumar, Joel S. Emer, Vivienne Sze
Comments: Published at ISPASS 2024
Subjects: Emerging Technologies (cs.ET); Hardware Architecture (cs.AR)
[9]  arXiv:2405.07061 (cross-list from cs.LG) [pdf, other]
Title: LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
Authors: Zeng Wang, Lilas Alrahis, Likhitha Mankali, Johann Knechtel, Ozgur Sinanoglu
Subjects: Machine Learning (cs.LG); Hardware Architecture (cs.AR); Cryptography and Security (cs.CR)
[10]  arXiv:2405.06676 (cross-list from cs.CL) [pdf, other]
Title: EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD
Authors: Bing-Yue Wu, Utsav Sharma, Sai Rahul Dhanvi Kankipati, Ajay Yadav, Bintu Kappil George, Sai Ritish Guntupalli, Austin Rovinski, Vidya A. Chhabria
Comments: Under review at Workshop on LLM-Aided Design (LAD'24)
Subjects: Computation and Language (cs.CL); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR)

Mon, 13 May 2024

[11]  arXiv:2405.06081 [pdf, other]
Title: Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis
Authors: Ismail Emir Yuksel, Yahya Can Tugrul, F. Nisa Bostanci, Geraldo F. Oliveira, A. Giray Yaglikci, Ataberk Olgun, Melina Soysal, Haocong Luo, Juan Gómez-Luna, Mohammad Sadrosadati, Onur Mutlu
Comments: To appear in DSN 2024
Subjects: Hardware Architecture (cs.AR); Distributed, Parallel, and Cluster Computing (cs.DC)
[12]  arXiv:2405.06127 (cross-list from cs.LO) [pdf, other]
Title: Efficiently Synthesizing Lowest Cost Rewrite Rules for Instruction Selection
Authors: Ross Daly, Caleb Donovick, Caleb Terrill, Jackson Melchert, Priyanka Raina, Clark Barrett, Pat Hanrahan
Subjects: Logic in Computer Science (cs.LO); Hardware Architecture (cs.AR)
[ total of 12 entries: 1-12 ]
[ showing up to 26 entries per page: fewer | more ]

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