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Computer Science > Hardware Architecture

Title: FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning

Abstract: This paper introduces the problem of learning to place logic blocks in Field-Programmable Gate Arrays (FPGAs) and a learning-based method. In contrast to previous search-based placement algorithms, we instead employ Reinforcement Learning (RL) with the goal of minimizing wirelength. In addition to our preliminary learning results, we also evaluated a novel decomposition to address the nature of large search space when placing many blocks on a chipboard. Empirical experiments evaluate the effectiveness of the learning and decomposition paradigms on FPGA placement tasks.
Comments: accepted by ISEDA2024
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG)
Cite as: arXiv:2404.13061 [cs.AR]
  (or arXiv:2404.13061v1 [cs.AR] for this version)

Submission history

From: Shang Wang [view email]
[v1] Thu, 11 Apr 2024 20:29:15 GMT (11606kb,D)

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