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Computer Science > Hardware Architecture

Title: Record Acceleration of the Two-Dimensional Ising Model Using High-Performance Wafer Scale Engine

Abstract: The versatility and wide-ranging applicability of the Ising model, originally introduced to study phase transitions in magnetic materials, have made it a cornerstone in statistical physics and a valuable tool for evaluating the performance of emerging computer hardware. Here, we present a novel implementation of the two-dimensional Ising model on a Cerebras Wafer-Scale Engine (WSE), a revolutionary processor that is opening new frontiers in computing. In our deployment of the checkerboard algorithm, we optimized the Ising model to take advantage of the unique WSE architecture. Specifically, we employed a compressed bit representation storing 16 spins on each int16 word, and efficiently distributed the spins over the processing units enabling seamless weak scaling and limiting communications to only immediate neighboring units. Our implementation can handle up to 754 simulations in parallel, achieving an aggregate of over 61.8 trillion flip attempts per second for Ising models with up to 200 million spins. This represents a gain of up to 148 times over previously reported single-device with a highly optimized implementation on NVIDIA V100 and up to 88 times in productivity compared to NVIDIA H100. Our findings highlight the significant potential of the WSE in scientific computing, particularly in the field of materials modeling.
Comments: 13 pages, 5 figures, plus supplementary information
Subjects: Hardware Architecture (cs.AR); Materials Science (cond-mat.mtrl-sci)
Cite as: arXiv:2404.16990 [cs.AR]
  (or arXiv:2404.16990v2 [cs.AR] for this version)

Submission history

From: Dirk Van Essendelft [view email]
[v1] Thu, 25 Apr 2024 19:20:44 GMT (8122kb,D)
[v2] Wed, 1 May 2024 19:47:16 GMT (9107kb,D)

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